1. Field of the Invention
The present invention relates to the testing of an integrated circuit design and in particular to the efficient compression of the output of such testing.
2. Related Art
Scan is a well-known design-for-test (DFT) technique to control test costs as well as facilitate silicon debug and fault diagnosis for integrated circuits. Notably, as the size and complexity of the designs of these integrated circuits increase, so too do the number and complexity of their corresponding scan test vectors. Indeed, even highly compacted vector sets generated with modern automatic test pattern generation (ATPG) require on-chip compression/decompression to reduce test cost. Combinational scan compression methods are particularly attractive for their simplicity and low overhead in area, timing, and design flow.
Combinational unload compression techniques exploit the low density of error values and can be fault model- and pattern set-independent. The main challenge for unload compressors is to ensure scan cell observation in the presence of unknown (X) values, i.e. values that cannot be accurately predicted by the simulation used during the ATPG process.
These X values can challenge any compression method, in particular deeply sequential compressors. Sequential unload compressors range from limited sequential depth registers to sequentially-controlled combinational data-path compressors. Combinational scan compression methods are particularly attractive for their simplicity and low overhead in area, timing, and design flow. However, these combinational scan compression methods are sensitive to X values.
Recent work that addresses this problem includes compressors that guarantee error detection in the presence of one X value, compressors tolerant of multiple unknown values, ECC-based compressors with special X-filtering hardware, low-area compressors with 2-X tolerance, and fully X-tolerant combinational compressors. An exemplary unload compressor is described in U.S. patent application Ser. No. 11/807,119, entitled, “Scan Compression Circuit And Method Of Design Therefor”, which was filed on May 25, 2007 for Synopsys, Inc., and which is incorporated by reference herein.
Unfortunately, compression can be significantly limited due to a high density of X values. For example, a high density of X values can result in the above-described X-masking, which then requires more scan patterns to test desired scan cells. In some cases, this increased number of scan patterns can negate any compression provided by the scan architecture. Therefore, a need arises for a method of increasing compression in IC designs with high X-densities.